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71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
DIO_DIR1[7:6,
3:0]
DIO_DIR2
[5:3,2:1]
DIO_0[7:4,2:0]
SFR91
[7:6,3:0]
SFRA1
[5:3,2:1]
SFR80
[7:4,2:0]
0
0
0
0
0
0
R/W
R/W
R/W
Programs the direction of pins DIO15-DIO14, DIO11-DIO8. 1 indi-
cates output. Ignored if the pin is not configured as I/O.
Programs the direction of pins DIO17-DIO16. 1 indicates output.
Ignored if the pin is not configured as I/O.
The value on the pins DIO7-DIO4 and DIO2-DIO1. Pins configured
as LCD will read zero. When written, changes data on pins confi-
gured as outputs. Pins configured as LCD or input will ignore write
operations. The pushbutton input PB is read on DIO_0[0].
DIO_1[7:6,3:0]
SFR90
[7:6,3:0]
0
0
R/W
The value on the pins DIO15-DIO14 and DIO11-DIO8. Pins con-
figured as LCD will read zero. When written, changes data on pins
configured as outputs. Pins configured as LCD or input will ignore
write operations .
DIO_2[5:3,1:0]
SFRA0
[5:3,1:0]
0
0
R/W
The value on the pins DIO17-DIO16. Pins configured as LCD will
read zero. When written, changes data on pins configured as out-
puts. Pins configured as LCD or input will ignore write operations.
DIO_EEX[1:0]
2008[7:6]
0
0
R/W
When set, converts DIO4 and DIO5 to interface with external
EEPROM. DIO4 becomes SDCK and DIO5 becomes bi-directional
SDATA. LCD_NUM must be less than or equal to 18.
DIO_EEX[1:0]
00
01
10
11
Function
Disable EEPROM interface
2-Wire EEPROM interface
3-Wire EEPROM interface
--not used--
DIO_PW
2008[3]
0
0
R/W
Causes WPULSE to be output on DIO6, if DIO6 is configured as
output. LCD_NUM must be less than 16.
EEDATA[7:0]
EECTRL[7:0]
ECK_DIS
SFR9E
SFR9F
2005[5]
0
0
0
0
0
0
R/W
R/W
R/W
Serial EEPROM interface data
Serial EEPROM interface control
Emulator clock disable. When one, the emulator clock is disabled.
This bit is to be used with caution! Inadvertently
setting this bit will inhibit access to the part with the
ICE interface and thus preclude flash erase and pro-
gramming operations . If ECK_DIS is set to zero, it should be done
at least 1000ms after power-up to give emulators and programming
devices enough time to complete an erase operation.
EQU[2:0]
EX_XFR
Reserved
EX_FWCOL
EX_PLL
2000[7:5]
2002[0]
2001[1]
2007[4]
2007[5]
0
0
0
0
0
0
0
0
0
0
R/W
R/W
Specifies the power equation to be used by the CE.
Interrupt enable bits. These bits enable the XFER_BUSY, the
Firmware Collision, and PLL interrupts. Note that if one of these
interrupts is to be enabled, its corresponding 8051 EX enable must
also be set. See the Interrupts section for details. Note that bit
2001[1] must always be 0.
FIR_LEN
2005[4]
0
0
R/W
The length of the ADC decimation FIR filter.
1-384 cycles, 0-288 cycles
When FIR_LEN =1, the ADC has 2.370370x higher gain.
V1.0
? 2005-2008 TERIDIAN Semiconductor Corporation
Page: 71 of 97
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